Tag: #make
What are automatic variables (dollar variables) in a
Makefile? Automatic variables in a Makefile, like
$@ for the target and $^ for the dependencies, reduce repetition in rules. 2016-12-07How do I set the C compiler in a
Makefile? Set the C compiler in
Makefile using predefined variable $(CC), which defaults to cc and can be redefined. 2016-12-05Make = Puppet 
2014-08-15
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